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WT8048
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DESCRIPTION
DPMS (Display Power Management Signaling) Detector for Green Monitor Aug. 31, 1995
The WT8048 is a 8 pin P-DIP package IC, designed for the application of Power Saving Monitor or Green Monitor.
As per DPMS proposal, the WT8048 provides a detective circuit of monitor power management for the convenience of designers in designing Power Saving Monitor.
FEATURES
{ Accepting two seperated H&V synchronous signals with positive/ negative polarity. { Capable of processing horizontal frequency between 0Hz to 100kHz, and vertical frequency between 0Hz to 100Hz.
{ Power Saving mode - It can detect the conditions of monitor to decide which will be selected as following: ON mode / STAND_BY mode / SUSPEND mode / OFF mode.
{ An Override mode is defined to override the DPMS function during the design, test, burn-in manufacture or diagnostic process if desired.
APPLICATION
{ DPMS mode's detection for Green Monitor
Weltrend Semiconductor, Inc.
2F., No. 24, Ind. E. 9th Rd., Science-Based Ind. Park, Hsin-Chu, Taiwan, R. O. C. Tel: 886-35-780241 Fax: 886-35-7704191
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ORDERING INFORMATION
Part No. WT8048 WT8048N1 WT8048N2 *WT8048N3 *WT8048N4 Package P-DIP 8L P-DIP 8L P-DIP 8L P-DIP 8L P-DIP 8L
WT8048
Description OSC with 32768Hz Crystal 1. OSC with external resistor 2. With mute function 1. OSC with external resistor 2. Without mute function 1. OSC with 3.58MHz resonator 2. With mute function 1. OSC with 3.58MHz resonator 2. Without mute function
Note: "*" means "not available".
PIN CONFIGURATION
WT8048N1 / N3
HIN 1 8 VDD HIN
WT8048 / N2 / N4
1 8 VDD
VIN
2
7
OFF STD_BY + SUSPEND MUTE
VIN
2
7
OFF
OSC
3
6
OSC
3
6
SUSPEND
VSS
4
5
VSS
4
5
STD_BY
2
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ABSOLUTE MAXIMUM RATING
ITEM Digital Supply Voltage Horizontal Sync. Input Voltage Vertical Sync. Input Voltage Power dissipation Operating Temperature Range Storage Temperature Range SYMBOL VDD VHS VVS PD TOPT TSTG VALUE 5.5 VDD(5)+0.3 VDD(5)+0.3 30 0 a0 7 -40 a25 1
WT8048
UNIT V VPP VPP mW J J
RECOMMENDED OPERATING CONDITIONS
ITEM Digital Supply Voltage Supply Current (Stand-by) Synchronous Input Voltage Low Synchronous Input Voltage High SYMBOL VDD(5) IP VIL VIH MIN. 4.5 TYP. 5 MAX. 5.5 1 0.8 5.5 UNIT V mA VPP VPP
2.4
4
3
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ELECTRICAL CHARACTERISTICS
A. WT8048
(VDD=5V, TOPT=24 J FOSC=32768Hz) ,
WT8048
ITEM Input Current (HIN, VIN), when VIN=5V Open Drain Output Low, when IOL = 6mA Open Drain Sink Current, when VOL = 0.4V Input Current (OSC), when VIN = 5V
SYMBOL MIN. IIN1 VOL VOL IIN3
TYP.
MAX. UNIT 5 g A 0.4 VPP 6 mA 5 g A
B. WT8048N1 / N2
(VDD=5V, TOPT=24 J FOSC= 450KHz) ,
ITEM Input Current (HIN, VIN), when VIN=5V Open Drain Output Low, when IOL = 6mA Open Drain Sink Current, when VOL = 0.4V Input Current (OSC), when VIN = 5V
SYMBOL MIN. IIN1 VOL VOL IIN3
TYP.
MAX. UNIT 5 g A 0.4 VPP 6 mA 15 mA
C. WT8048N3 / N4
(VDD=5V, TOPT=24 J FOSC= 3.58MHz) ,
ITEM Input Current (HIN, VIN), when VIN=5V Open Drain Output Low, when IOL = 6mA Open Drain Sink Current, when VOL = 0.4V Input Current (OSC), when VIN = 5V
SYMBOL MIN. IIN1 VOL VOL IIN3
TYP.
MAX. UNIT 5 g A 0.4 VPP 6 mA 5 g A
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PIN DESCRIPTION
Pin No.
WT8048N1 /N3 WT8048/ N2/N4
WT8048
Name HSIN VSIN OSC
Function Input terminal of horizontal synchronous signal Input terminal of vertical synchronous signal A clock generator circuit is built into the chip. So, if a resonator is connected to OSC pin and ground, a clock signal can be obtained. Ground Indicate in Stand_By mode Indicate in Mute mode Indicate in Suspend mode Indicate in Suspend and stand_By mode Indicate in Off mode 5 volts power supply
Structure of Terminal
Input, TTL compatible Input, TTL compatible Input
1 2 3
1 2 3
4 5
4 5 6
6
7 8
7 8
VSS STD_BY Mute Suspend Suspend + STD_BY Off VDD
Output, open drain Output, open drain
Output, open drain
5
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APPLICATION DESCRIPTION
DPMS (Display Power Management Signaling) Dection
WT8048
As per DPMS proposal WT8048 provides Monitor Power Management Detection Circuit for the convenience of monitor designers in designing power saving minitors, or the so called "Green Monitors". Please refer to the table 1 as below for power states defined in the DPMS. DPMS requires at least 5 seconds delay before transition from ON state to any power saving state, to avoid unintentionally entering a power saving state during display resoultion changes and timing mode changes. And it can be done instaneously, for the transition between any power saving state.
State On Stand-By Suspend Off
Table 1 Display Power Management Summary Signals DPMS Power Compliance Horizontal Vertical Video Savings Requirement Pulse Pulses Active Mandatory None No Pulses Pulse No Pulses Pulses No Pulses No Pulses Blanked Blanked Blanked Optional Mandatory Mandatory Minimal Substantial Maximum
Recovery Time Not Applicable Short Longer System Dependent
* "No Pulse" represents the frequency of Hsin or Vsin less than or equal to 10Hz, but "Pulses" represents that frequency of Hsin greater than or equal to 15KHz (WT8048), 10KHz (WT8048N1 / N2 / N3 / N4) and Vsin greater than or equal to 40Hz.
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The Way WT8048 implements VESA DPMS
WT8048
As shown on Table 2, when H_SYNC / V_SYNC signals transition from ON state to any one of the three power saving state, WT8048 will delay 5.9 seconds to meet the VESA DPMS requirement: the minimum 5 seconds delay to avoid unintentionally entering a power saving state during display resolution and timing mode changes. If during this delay time period, H_SYN and V_SYN signals return to ON state, then all three power management pins will remain ON state. If power management state of H_SYNC and V_SYNC prolong for more than 5.9 seconds, then these three power management pins will change to the corresponding states. While changing from any power saving state back to ON state will take about 0.368 second for H_SYNC / V_SYNC pulse checking. And transition between any power saving state will be done immediately.
Table 2: The truth table of Power Saving Detector MODE ON STAND_BY SUSPEND OFF OVERRIDE HSIN Pulses No Pulses Pulses VSIN STD_B Y 1 0 0 0 1 SUSPEND 1 1 0 0 1 OFF 1 1 1 0 1
Pulses Pulses No Pulses No Pulses No Pulses No Pulses No Pulses Manually Power On
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Synchronization Signals
WT8048
The basis of DPMS standard is the condition of the synchronization signals to the display. Two conditions are defined: pulses and no pulses. { PULSES pulses for the Horizontal Sync. Signal are defined as greater than 10KHz repetition frequency and pulses for the Vertical Sync. Signal are defiened as greater than 40Hz repetition frequency. { NO PULSES No pulses is defined as less than 10Hz repetition frequency with less than 25% duty cycle Please refer to the Fig. 1 for the way WT8048 Implement pulses/ no pulses state, between 10Hz and 15KHz / 10KHz, 10Hz and 40Hz. WT8048 use hystersis technique to stable state in between.
STATE P NP H_SYNC FREQUENCY
T
10 Hz
f
f = 15k for WT8048 T = 10k for WT8048N1/N2/N3/N4
STATE P NP V_SYNC FREQUENCY
10 Hz
40 Hz
Figure 1: pulses / no pulses state implementation
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WT8048
OVERRIDE mode To initiate Override, both the horizontal and vertical sync signals shall be in the no pulses condition when the display is manually powered on. This condition should be maintained during the entire time Override is required. As soon as pulses are detected on either horizontal or vertical sync signal. The display shall enter DPMS operation. Three power management pins are open drain structure and active low. If you do not need all those three power saving states in your design. You can just short two or three pins of the pins: for example, by shorting pin STD_BY and pin Suspend, you will have only two power saving stated, that is OFF and Suspend states, so you have three states total, including ON state.
TYPICAL APPLICATION CIRCUIT
WT8048:
5V HSIN 680 10K 680 10K 10K 10K
1 2
VCC
1
8
5V 3.3M 10K 945
VSIN
2
7
3 4
6 5
32768Hz
470P
NOTE: 1. 2. Transistor: 2SC945 A ] 300 C > VDD: +5V 10%
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WT8048N1 / N2:
5V HSIN VDD 68K or 75k VSIN 10k 10p 10k 100p 1 8 Rx 2 7 VCC
WT8048
(Pin 5 pull up Rx for N2 only)
3 4
6 5
NOTE:
Connect pin 3 with single resistor for RC oscillation.
WT8048N3 / N4:
5V HSIN 10k 10p 10k 100p 1 8 VCC
VSIN
2
7
3 3.58 MHz 4
6 5
NOTE: 1. 2. Connect pin 3 with 3.58MHz resonator have good precision of delay time, frequency division point. This package is not available for production.
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